The invention is in the field of semiconductor devices and more particularly of protection devices incorporated on integrated circuits. The protection devices are used in protecting the electronic apparatuses from voltage and current transients, for example constructed of a silicon-controlled rectifier.
It is well known that integrated circuits manufactured by using CMOS (complementary metal-oxide-semiconductor) fabrication technology are readily influenced by electrostatic discharge (ESD) induced, for example, from contact with a human body. When ESD occurs, high voltage transient (or high current transient) flows into the integrated circuit chip and causes physical damages therein, for example in the form of destruction of a thin gate oxide layer, or causing shorting of channels.
A number of techniques have been developed for protecting semiconductor devices, including bipolar transistors, field effect devices, and integrated circuits, from damaging ESD Effects. Such protection techniques have commonly taken the form of diode or transistor circuits located at the input and output regions of the integrated circuit chip.
As one of the popular forms of protection devices, silicon-controlled rectifiers (SCRs) have been utilized in protecting integrated circuits. The lower triggering voltage of the SCR is advantageous in enhancing protection performance against electrical transient damage such as electrostatic discharge (ESD). Such SCR approaches are proposed in a number of references, e.g., U.S. Pat. Nos. 4,400,711, 4,484,244, 4,633,283, or 5,012,317. Referring to FIG. 1A, which illustrates a known structure of the low-voltage SCR (e.g., as disclosed in U.S. Pat. No. 5,012,317), when the voltage of the external pad becomes higher, the parasitic PNP bipolar transistor Q2 is turned on. The transistor Q2 provides holes to the substrate 1, and the base-to-emitter voltage of parasitic NPN bipolar transistor Q1 becomes higher due to an influx of the holes, and then the transistor Q1 becomes turned on. Next, the excessive ESD current is discharged through a SCR circuit formed of the resulting PNPN path such that electrons from Vss terminal 13 are injected to the N-type well 3 through the substrate 1. The NP junction formed of the N-type well 3 and the P-type substrate 1 is caused to be reverse-biased, and a breakdown voltage at the NP junction is regarded to a triggering voltage (or a threshold voltage) of the SCR.
As CMOS circuits continue to become more highly integrated, and therefore decrease in size, the SCR shown in FIG. 1A becomes less effective as a protection device. While the range of the triggering voltage is generally positioned from 25V to 70V, a substantial part appears at the higher level the range because triggering throughout the SCR occurs at least after the breakdown of the NP junction. Thus, as density increases, it is more likely for the circuit to become damaged by the transient before the SCR is activated, due to the high triggering voltage. The triggering voltage corresponding to the SCR of FIG. 1A, for example, would approach about 70V.
Lowering the triggering voltage of a SCR has been considered in the past, for example as disclosed in U.S. Pat. No. 4,939,616xe2x80x94Rountree, and U.S. Pat. No. 5,072,273xe2x80x94Avery. In the Rountree example, an N+ region is formed at the interface of the N-type well (e.g., 3 in FIG. 1A) and the substrate (e.g., 1 in FIG. 1A), so that a breakdown occurs at the N+ region, in order to lower the triggering voltage thereof. The example given in the Avery reference, as shown in FIG. 1B, pulls down the triggering voltage of the SCR by electrically binding the N+ region 7 and the P+ region 5, both formed in the substrate 1, in addition to the N+ region 12 (or a P+ region) formed over the N-type well 3 and substrate 1. Although these two examples are useful for confronting transient voltage or current between an input pad and ground, i.e., a positive transient, throughout the PNPN junction, they are not suitable for providing high-performance ESD protection against a negative transient occurring between an input pad and a power supply voltage terminal. Assuming that, in the condition of an ESD protection between an input signal terminal (e.g. input pad) and a voltage supply terminal (e.g. power supply voltage), the reference numerals 13 and 15 are each assigned to the input pad and the power supply voltage respectively, an NPNP junction for distributing the negative transient cannot be formed therethrough because the substrate 1 and the input pad 13 are forced to be in a short circuit with them.
Accordingly, the primary object of the invention is to provide a silicon-controlled rectifier having a reduced trigger voltage.
It is another object of the invention to provide a silicon-controlled rectifier having a reduced turn-on voltage so as to be consistent in operating with a low voltage therein.
It is another object of the invention to provide a silicon-controlled rectifier capable of protecting a voltage or current transient in a bi-directional discharging loop.
It is another object of the invention to provide a silicon-controlled rectifier adaptable to a CMOS fabrication process without additional mask steps, having a reduced triggering voltage.
In order to attain the above objects, according to an aspect of the present invention, a silicon-controlled rectifier of the invention includes: a semiconductor substrate having a first conductivity; a semiconductor region formed in the substrate, having a second conductivity; a first region formed in the substrate, having the first conductivity and being spaced apart from the semiconductor region; a second region formed in the substrate, having the second conductivity and being spaced apart from the semiconductor region and first region; a third region formed in the substrate, having the second conductivity and being spaced apart from the semiconductor region, the first and second regions; a fourth region formed in the semiconductor region, having the second conductivity and being connected to the third region through a conductive material; a fifth region formed in the semiconductor region, having the first conductivity and being spaced apart from the fourth region; and a sixth region formed in the semiconductor region, having the second conductivity and being spaced apart from the fourth and fifth regions. The first and second regions are connected to a first terminal, and the fifth and sixth regions are connected to a second terminal. A gate layer formed to be laid over a surface between the second and third regions and connected to the first terminal.
In the case of that the third and fourth regions have the first conductivity, the fourth region being also connected to the third region through a conductive material, the first and second regions are connected to the first and second terminals, respectively, and the fifth and sixth regions are connected to a third terminal. The gate layer, provided over the surface between the second and the third regions and connected to the first terminal in the above case, is replaced a gate layer which is provided over a surface between the fourth and fifth regions and connected to the third terminal.
In another aspect of the invention, a silicon-controlled rectifier includes: a semiconductor substrate having a first conductivity; a semiconductor region having a second conductivity; a first region formed in the substrate, having the first conductivity; a second region formed in the substrate, having the second conductivity; a third region formed in the semiconductor region, having the second conductivity and being spaced apart from by a predetermined distance from a boundary between the substrate and semiconductor region; a fourth region formed in the semiconductor region, having the first conductivity; a fifth region formed in the semiconductor region, having the second conductivity; and a sixth region formed in the substrate, the sixth region having the first conductivity and being spaced apart by a predetermined distance from the boundary between the substrate and semiconductor region.
When a positive transient inflows thereto, the first and second regions are connected to a first terminal, and the fourth and fifth regions are connected to a second terminal. When a negative transient inflows thereto, the first and second regions are connected to the first and second terminals, respectively, and the fourth and fifth regions are connected to the third terminal.
The present invention further provides bi-directional discharging paths for the ESD protection. For this purpose, a silicon-controlled rectifier includes: a semiconductor substrate having a first conductivity; a first well formed in the substrate, having a second conductivity; a first region formed in the first well, having the first conductivity; a second region formed in the first well, having the second conductivity and connected to a first terminal together with the first region; a second well formed in the substrate, being spaced apart from the first well; a third region formed in the second well, having the second conductivity; a fourth region formed in the second well, having the first conductivity and being connected to a second terminal together with the third region.
For the purpose of lowering the triggering voltage of the bi-directional discharging SCR, the silicon controlled rectifier further includes: a fifth region formed in the first well, having the second conductivity and being spaced apart from, or adjacent to a boundary between the substrate and the first well by a predetermined distance; and a sixth region formed in the second well, having the second conductivity and being spaced apart from a boundary between the substrate and the second well by a predetermined distance. The fifth and sixth regions may optionally be comprised of the first conductivity.
In another aspect, a silicon-controlled rectifier includes: a semiconductor substrate having a first conductivity; a first well formed in the substrate, having a second conductivity; a first region formed in the first well, having the first conductivity; a second region formed in the first well, having the second conductivity and connected to a power supply voltage together with the first region; a second well formed in the substrate, being spaced apart from, or adjacent to the first well; a third region formed in the second well, having the second conductivity; a fourth region formed in the second well, having the second conductivity and being connected to an input pad together with the third region; a fifth region extending over the first well and the substrate, having the second conductivity; and a sixth region extending over the second well and the substrate, having the second conductivity.
In yet another aspect for the bi-directional discharging path for the ESD protection, a silicon-controlled rectifier includes: a semiconductor substrate having a first conductivity; a first well formed in the substrate, having a second conductivity; a first region formed in the first well, having the first conductivity; a second region formed in the first well, having the second conductivity and connected to a first terminal together with the first region; a second well formed in the substrate, being spaced apart from the first well; a third region formed in the second well, having the second conductivity; a fourth region formed in the second well, having the first conductivity and being connected to a second terminal together with the third region; a fifth region formed in the first well, having the second conductivity and being spaced apart from a boundary between the substrate and the first well by a predetermined distance; a sixth region formed in the second well, having the second conductivity and being spaced apart from a boundary between the substrate and the second well by a predetermined distance; a seventh region formed in the substrate, having the first conductivity and being spaced apart from a boundary between the substrate and the first well by a predetermined distance; and a eighth region formed in the substrate, having the first conductivity and being spaced apart from a boundary between the substrate and the second well by a predetermined distance.